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How does the PLL work?

Published:2019/10/28 17:48:14 Visits:
1. How does the PLL work?

The phase-locked loop is generally composed of a PD (phase detector), an LPF (loop filter), and a VCO.

Some students may have to ask: "Since the VCO can already output the frequency after a given voltage, why not use it directly?"

In fact, it can be used like this. Now some crystal oscillators will optimize the frequency for a fixed frequency. For example, some VCXO (external VCO) of 122.88MHz, these crystal oscillators have a characteristic, phase noise at this frequency. Performance optimization is particularly good. But crystals are generally difficult to make the frequency high. The VCO that is often used in our PLL, the frequency change intermediate frequency is GHz, and the variation range is several hundred megahertz. If an open-loop VCO (without PLL structure) is used, the phase signal noise is particularly bad, and Voltage variations (such as noise, temperature effects) cause the VCO's output frequency to drift.

Therefore, it has been proposed to use a structure such as a PLL to output a relatively stable (LOCKED) frequency. The main idea is to use a relatively clean phase reference frequency to create a closed-loop structure to obtain a relatively high-frequency phase with a relatively clean phase.

As shown in the figure above, the input signal passes through the phase detector. When the phase of the feedback signal and fref are the same, the PD outputs a constant voltage value (actually the current is output by the CP), which makes the system stable.

If we think of PD as a multiplier, then there is a reference input signal.

The angular frequency of the feedback input is:

N is generally expressed as the division ratio of the feedback DIV.

The feedback input signal is:

The multiplication of the two can obtain two components of high frequency and low frequency according to integration and difference. The high frequency part will be filtered by the LPF. So only the low frequency part is left.

For the low frequency part, the phase is recorded as:

To make the system stable, that is, the phase is constant, the phase can be derived from the time t, and when it is equal to 0, the two phases can be considered to be the same. Generally put

See the random start-up phase of the two clocks and remain unchanged after power-on. So have

When the derivative is 0:

At this time

If the reference frequency is 10 MHz and N is 350, the frequency output of 3.5 GHz can be obtained. Of course, the premise is that the PLL's VCO supports this band.

Of course, for the current chip, there is also a frequency divider or frequency multiplier before the reference frequency input of the discriminator, which is generally recorded as R.

2. PLL loop bandwidth analysis

The most important aspect of the phase-locked loop design is the design of the LPF. In general, the topology of the LPF is fixed, nothing more than the difference in order, some PLL chips will have built-in LPF, adjust the bandwidth by configuring the size of R and C, but generally for performance and space constraints More PLLs put the loop filter outside the chip.

Many beginner PLLs will encounter a problem. How is the loop bandwidth of the PLL designed? Generally speaking, the narrower the LPF, the longer the locking time, the better the suppression of some spurs, but at the same time, it should not be too narrow to prevent the suppression of VCO noise.

Let's first look at the phase noise equation of the PLL:

Among them, FOM represents the noise floor of the phase detector. It should be noted that the DIV is not the same thing as the DIV mentioned above. The DIV here refers to the division factor of the clock divider. For some systems requiring multiple clocks, the splitter can output the locked VCO as a multi-clock, but set a specific crossover value for the different clocks required for different chips before output. It can be seen that when the phase-detection frequency Fpfd is doubled, the phase noise can be reduced by 3dB. Therefore, if the PLL can be used, it is recommended to use a relatively high phase-detection frequency to improve the phase noise performance of the PLL, but it is also necessary to consider the PD of the system Fpfd. The performance, in general, the phase discrimination frequency of the PD has a certain range.

Let’s take a look at the phase noise map that we often see.

In general, the noise in the low frequency part of the noise is contributed by the phase noise of the reference frequency, so it is necessary to use a good reference frequency. The noise of the IF section is contributed by the phase detector of the PLL, after which the high frequency is substantially contributed by the VCO.

If there is spurs in the band, it is generally preferred to adjust the LPF so that the spurs fall out of the band and automatically filter out. How do some of the strays fall within the band? In general, the spurs come from the low-frequency noise on the power supply. This has to be checked from the power supply. I will elaborate on the third part.

Narrow-band LPF can be used to suppress in-band noise, but "How can LPF be too narrow to prevent insufficient suppression of VCO noise?" Here we have to start with a negative feedback system.

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